Welcome to Pydrofoil’s documentation!¶
Pydrofoil is an experimental emulator-generator for ISA models written in Sail. It can generate emulators for RISC-V, ARM, CHERIoT based on their respective Sail models. The Pydrofoil-generated emulators achieve fast performance by doing dynamic binary translation (aka just-in-time compilation) from guest instructions into host machine instructions. It’s built on top of the RPython meta-jit compiler and reuses all its optimizations, backends, etc. Performance is typically an order of magnitude better than the emulators generated by Sail.
To get started with the RISC-V emulator, please consult Building Pydrofoil from source.